This invention relates generally to semiconductor memories and more particularly to content addressable memories.
Content addressable memories (CAMs) are frequently used for address look-up functions in Internet data routing. For example, routers used by local Internet Service Providers (ISPs) typically include one or more CAMs for storing a plurality of Internet addresses and associated data such as, for instance, corresponding address routing information. When data is routed to a destination address, the destination address is compared with all CAM words, e.g., Internet addresses, stored in the CAM array. If there is a match, routing information corresponding to the matching CAM word is output and thereafter used to route the data.
A CAM device includes a CAM array having a plurality of memory cells arranged in an array of rows and columns. Each memory cell stores a single bit of digital information, i.e., either logic zero or logic one. The bits stored within a row of memory cells constitute a CAM word. During compare operations, a comparand word is received at appropriate input terminals of a CAM device and driven into the CAM array using comparand lines to be compared with all the CAM words in the device. For each CAM word that matches the comparand word, a corresponding match line signal is asserted to indicate a match condition. If the comparand word matches more than one of the CAM words, the match line corresponding to each of the matching CAM words is asserted, and a xe2x80x9cmultiple matchxe2x80x9d flag is also asserted to indicate the multiple CAM words is asserted, and a xe2x80x9cmultiple matchxe2x80x9d flag is also asserted to indicate the multiple match condition. The match line signals from each CAM block are combined in a priority encoder to determine the address of the highest-priority matching CAM word, i.e., the CAM index. Associative information corresponding to the CAM index stored in, for instance, an associated RAM, may also be provided.
A single CAM device can be used to store multiple tables each storing and maintaining different classes of data. All entries, however, typically participate in a compare operation. This can cause an undesirable amount of power to be drawn during the compare operation. It would be desirable to limit a search to only those entries associated with a particular class of data to reduce power consumption during the operation.
In a typical CAM device, the width of the data word is fixed according to the number of memory cells per row of the CAM array. U.S. Pat. No. 5,440,715 describes a technique for expanding the width of the data words beyond that of a single row of CAM cells. This inter-row configurability provides flexibility in the use of the single CAM array to store data words larger than that available in a single addressable row of CAM cells.
It would be desirable to have a CAM system that includes intra-row configurability to provide additional flexibility in the use of a single CAM array to be used in multiple array configurations. Intra-row configurability is the ability to access and operate upon one or more segments of rows of CAM cells.
A method and apparatus are disclosed that may be used to partition a CAM device having a plurality of CAM blocks into a number of individually searchable partitions, where each partition may include one or more CAM blocks of the CAM device. In accordance with one embodiment of the present invention, each CAM block is connected to a block select circuit that stores a class code indicating what class or type of data is stored in the block. The same class code may be stored in any number of the block select circuits to define a partition as including the corresponding number of CAM blocks. During compare operations between a comparand word and data stored in the CAM device, a search code is provided to the block select circuits. Each block select circuit compares the search code with its class code and, in response thereto, selectively enables or disables the corresponding CAM block for the compare operation. In some embodiments, the block select circuit enables the corresponding CAM block if the search class matches the class code and, conversely, disables the corresponding CAM block if the search code does not match the class code.
In one embodiment, the block select circuit disables a corresponding CAM block by driving the comparand lines of the CAM block to a predetermined state to preclude the comparand word from being driven onto the comparand lines during the compare operation. By driving the comparand word only on the comparand lines of the selected (i.e., enabled) CAM blocks during the compare operation, present embodiments not only allow for selective searching across CAM blocks according to class codes, but also reduce power consumption in un-selected (i.e., disabled) CAM blocks during such selective compare operations.
A CAM system having intra-row configurability is also disclosed. For one embodiment, the CAM system includes a CAM array having a number of rows of CAM cells each segmented into row segments. Each row segment includes a number of CAM cells coupled to a corresponding match line segment. Individual row segments or groups of row segments are uniquely addressable by address logic in response to configuration information that indicates a width and depth configuration of the CAM array. The configuration information may be stored in a configuration register. Data may be communicated with an addressed row segment or group of row segments using data access circuitry. Priority encoding circuitry may be included to generate the address of a row segment or group of row segments that stores data matching comparand data in response to the configuration information. Match flag logic may also be included to determine when comparand data matches data stored in one of the row segments or one of the groups of row segments in response to the configuration information. Additionally, multiple match flag logic may be included to determine when comparand data matches data stored in each of a plurality of row segments and to determine when comparand data matches data stored in each of a plurality of groups of row segments in response to the configuration information.
In one embodiment, a CAM system includes multiple CAM blocks each having an associated block select circuit. Each of the CAM blocks is configurable to store data words having a width determined according to a configuration value and is responsive to a block select signal from the associated block select circuit to either participate or not participate in a compare operation. Each select block select circuit compares an input class code with a stored value and either asserts or deasserts the block select signal for the associated CAM block according to the comparison result.
These and other embodiments, features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.